The present invention relates generally to switch logic and, more particularly, to VLSI arithmetic parallel counters, binary partial product reduction trees, and parallel structured full array multiplier schemes.
Modulo arithmetic operations, which produce a remainder and a quotient, also called carrys, given two small integers, are the basis for formation and representation of the most important number systems such as binary and octal. In the prior art, remainders and quotients were represented by binary signals. The logic of this invention employs types of signal, called state signals, in addition to the binary signals. The aforementioned operations, in accordance with the new logic, are implemented using novel electronic components called shift switches: C4 and (7,3) parallel counter and compressor families. The concept of the shift switches stems from the concept of dynamic reconfigurable architectures..sup.4-6,9
Multiplier schemes of the prior art use full adders, such as Wallace-Dadda schemes, for the reduction of a partial product matrix. Various (4,2) and (7,3) configurations are also used..sup.1-3, 11-19, 21 They typically reduce a partial product matrix into two binary numbers.
It would be advantageous to provide a multiplier scheme that employs only shift switch devices with C4 and C4 based (7,3) families as building blocks.
It would also be advantageous to provide such a scheme to reduce the partial product matrix into a binary number and a number represented by a sequence of state signals.
It would further be advantageous to provide such a scheme with VLSI architecture that is highly regular and modular with repeatable interconnection structures, one in binary tree form and the other in linear array form.
It would also be advantageous to provide such a scheme that is fast, requires a compact VLSI area, and dissipates less power.